This translates to provide innovative solutions enabling: test time (cost) reduction and test data quality improvement combined with product quality and reliability improvement
We assist our customers to considerably cut down on test costs and realize the best products at the lowest cost. We provide intelligent measurement modules and related solutions that allow exploiting current testing (IDDQ, ISSQ, ICCQ, IDDT, IDDX, ISSX, ICCX) to its full extend.
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DSP Valley : a growing network and technology network organization of high-tech companies that are focusing on the design of hardware and software technology for digital signal processing systems. DSP Valley groups members of different kinds: universities, research institutes and industrial companies (from small startups up to large international groups). DSP Valley members cooperate to provide optimal and integrated solutions for their customers, ranging from hardware to
software, from using general purpose DSPs to custom VLSI or FPGAs.
For more information : www.dspvalley.com
Setnet: a network of companies, organizations and individuals active in the field of semiconductor test. SETNET has been established to raise the profile of semiconductor test, to encourage collaboration between industry and academia and to provide some of the necessary tools in terms of products and services for members as well as an infrastructure for the dissemination of information based services. The network is coordinated by tCORE Ltd (www.tcore.co.uk).
For more information : www.setnet.org
ESTS: a trade group for companies serving fabless and traditional semiconductor companies.
ESTS is a community of experts serving semiconductor compa nies that are outsourcing verification and test activities. The ESTS consists of a growing community of focused experts, and specialized tool vendors.
As Traditional and Fabless Semiconductor companies focus resources on unique IP design, other aspects of semiconductor development and manufacture are outsourced. This includes verification, product engineering & test, and specialized digital design. Large EDA and Hardware companies are also focusing their resources on large volume, high cost
tools, leaving specialized verification and test tools to smaller ESTS member companies.
The goal of the ESTS is to promote the interests of small companies who have focused their resources on some aspect of semiconductor verification and test that is or can be outsourced.
For more information: www.ests.net
was born in Brugge, Belgium on March 11, 1963. He received the Electrical Engineering Degree (MSc) in Electronics from KIHWV (Technical University of Oostende) in 1987. After performing his military duties, he joined the KIHWV, now KHBO, as a staff member of the microelectronics department (associated lab of IMEC), where he lectured ASIC-design, testability and design for test, IC testing, the use of CAD-tools and informatics. When working at KHBO he conducted, stimulated and coordinated research in the areas of integrated circuit design, test of integrated circuits and design for test. He was co-operating with Alcatel Bell and Alcatel Microelectronics in the development of
off-chip current monitors and Iddq test strategies. He was also involved in several European Research and education projects as well as in national funded projects. He was the co-ordinator of the Copernicus project UBISTA, focussing on supply current based (self-) test strategies for analog and mixed signal circuits.
He received the Ph.D. Degree in Electronic Engineering, from the University of Hull (UK) in February 1997, after successfully defending a thesis on methods to enhance IC testability and the application of Iddq testing.
In 1999, he joined IMEC as a researcher and at the end of 1999 he took the initiative to set up the KHBO/IMEC spin-off company Q-Star Test, focussing on marketing supply current test solutions. Hes currently President & CEO of Q-Star Test and guest professor at KHBO.
He is a member of the IEEE, was a member of the IEEE QTAG (Quality Test Action Group) workgroup served on the Program Committee of CSS96, EDS97, EDS'98 and ECS'99, served on the Program Committee of the IEEE European Test Workshop (ETW), serves on the Program Committee of the IEEE European Test Symposium (ETS), serves on the Program Committee of the Design, Automation and Test in Europe (DATE) conference, serves on the Program Committee of the IEEE VLSI Test Symposium (VTS), serves on the Program Committee of the IEEE International On-Line Testing Workshop (IOLTW), serves on the Organizing & Program Committee of the IEEE International Defect based Testing Workshop (DBT), is member of the Program Committee and Steering Committee of the Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS) and acts as a reviewer for the International Test Conference (ITC) and the JETTA magazine. He was General Chair-Organiser of CTAMS'98, he was Program vice Chair for ETW'99 and ETW2002, Program Chair of DDECS'2000, Publicity Chair of ETW2000, DBT2001, DBT2002 and ETW2001. He is also an active member of the IEEE-CS ETTTC (European group of the Test Technology Technical Committee) as well as of the TTTC and responsible for the set up of IEEE-ETTTC one-day Hot Topic workshops on test and design for test themes.
He delivered active contributions to several national and international conferences and workshops. He authored/co-authored so far more than 75 papers of which more than 40 papers on current monitors and current-based test strategies and holds 6 patents on Iddq monitors and quiescent supply current measurement techniques.
Expertise / Know-How
IC and ASIC design, IC test, Test strategy development and improvement, Design for Test methodologies (SCAN, BIST, Boundary Scan, …) and application, Fault models, fault
grading, Test vector generation, ATPG, Digital / Mixed-signal circuit testing, memory
testing, (supply) current based test, (supply) current based Design for Test, Iddx monitor design and development for
on-chip and off-chip applications, Iddq, Iddt, Iddx, BICS, Iddx application strategies, reliability screens, quality screening, 0ppm support.
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When Cost reduction, Test and Data quality are Keys
When Reliability is of Concern
When Quality of Engineering means Value
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European Test Symposium
27 - 31 May 2019
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