The symbol IDDQ has a double meaning. IDDQ is used to refer to the quiescent supply current and IDDQ is also used to refer to a test method that is based on taking quiescent supply current (IDDQ) measurements.
The quiescent supply current (IDDQ)is the current that flows when the device is in a stable (and repeatable) state and is equal to the leakage current for logic structures and the combination of leakage and bias currents in the more general case.
IDDQ as a test method is a test technique based on measuring the Quiescent supply current of the device under test. A distinction needs to be made between application to technologies where the leakage current is negligible and application to technologies were the leakage current cannot be neglected. The IDDQ test offers a screen that allows for quick identification of defective parts, during both wafer and final test.
IDDQ testing is linked to the history of CMOS IC design and fabrication. In 1963 Frank Wanlass (Fairchild Semiconductor) originated and published the concept of complementary-MOS (CMOS) logic circuitry. It occurred to him that a CMOS circuit would use very little power and that in standby, it would draw practically nothing - just the leakage current. The concept of IDDQ testing (validating circuits by measuring and observing their quiescent supply current) and its application to CMOS circuits was developed and demonstrated by Mark W. Levi in his ITC1981 paper (CMOS is most Testable, Proceedings of ITC81, pp. 217-220). It is therefore a fact that CMOS circuits with increased leakage current are defective.
Traditionally IDDQ - as a test approach - is seen as an approach whereby measurement results are compared against a predefined pass/fail threshold. For the Traditional IDDQ approach this threshold is the same for all tested devices, thereby assuming a clear distinction between leakage and defect currents. The traditional decision criterion - which is valid for technologies with low leakage currents - is based on the fact that a CMOS circuit does not draw any significant current when in a stable situation. In a quiescent state, only the leakage current flows, which is in most cases can be neglected. The fact that under certain conditions a significant current flows when the device under test is in a quiescent state, indicates the presence of a manufacturing defect in the circuit. Such a defect which causes a current increase, may have a direct influence on the functionality of the circuit (functional failure) or may affect the lifetime and reliability of the circuit negatively ((early) lifetime failure). Further info on IDDQ and limit setting can be found in the TRUE IDDQ section.
For newer technologies, where the leakage current cannot be neglected, a similar observation
holds, when the base leakage that cannot be neglected needs to be considered as an offset level. The fact that under certain conditions there is an increase in the current flowing when the device under test is in a quiescent state, indicates the presence of a manufacturing defect in the circuit. Such a defect which causes a current increase, may have a direct influence on the functionality of the circuit (functional failure) or may affect the lifetime and reliability of the circuit negatively
((early) lifetime failure). By using a relative decision criterion (based on the comparison of the measured current to the base leakage current) defects can be screened reliably and effective, even in the presences of large background currents, provided suitable measurement tools are used.
A large number of publications exists that deal with IDDQ, ISSQ and IDDT technology, that address the application of these technologies or that discuss the use and application of IDDX measurement modules.
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